The present inventive concept relates to semiconductor memory devices and more particularly to non-volatile memory devices programmed using an incremental step pulse programming (ISPP) scheme. The inventive concept as relates to methods for programming non-volatile memory devices.
Semiconductor memory devices include volatile and non-volatile types of memory. Volatile memories general enjoy fast read/write speeds, but lose stored data in the absence of applied power. In contrast, non-volatile memories generally operate at slower read/write speeds, but retained stored data in the absence of applied power. Due to this ability to retain stored data in the absence of applied power, non-volatile memory has been increasingly used in a variety of host devices to store programming (or system) data as well as payload (or user) data.
Nonvolatile memory includes a variety of memory types including phase-change random access memory (PRAM), mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). However, MROM, PROM, and EPROM types of nonvolatile memory do not provide ready access to data since read/write operations are slow and cumbersome. On the other hand, EEPROM enables electrical erase and write operations and is thus increasingly used in applications which require continuous data update or the use of auxiliary memory devices.
Among other types of EEPROM, so-called flash EEPROM or “flash memory” is capable of being fabricated with a very high degree of memory cell integration. Thus, flash memory is commonly used to implement large-capacity auxiliary memory devices, and has been increasingly incorporated into electronic devices, such as digital cameras, digital camcorders, digital music players, mobile telephones, etc. These host devices require large data storage capacity and high performance re-programmability, but must also be manufactured with a compact size. Flash memory generally includes NAND-type and NOR-type flash memory.
The data stored in a memory cell of flash memory, including both single level and multi-level memory cells, is defined by a corresponding threshold voltage of the memory cell. A program operation defines this threshold voltage. In many conventional program operations, the threshold voltage of a memory cell is incrementally defined using an ISPP scheme.
Generally speaking, when a memory cell is programmed using an ISPP scheme, a program voltage applied to a word line connected to the memory cell is gradually increased through a sequence of step increments until the program voltage reaches a level sufficient to properly program the target memory cell. Since the voltage program is a relatively high voltage, it may cause the conventionally understood “program disturb” in memory cells adjacent to the target memory cell. The program disturb is essentially a phenomenon in which the threshold voltage(s) of one or more memory cell(s) nearby the target memory cell is undesirably modified by the program voltage being applied to the target memory cell. As will be appreciated, when the program voltage is step-increased through an ISSP scheme, the risk of a program disturb occurring increases. Therefore, a programming method capable of reducing the risk of program disturbs is desired.